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UTC X3211
LINEAR INTEGRATED CIRCUIT
FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION
DESCRIPTION
The UTC X3211 is designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc. with a minimum of external components.
SSOP20(150mil)
FEATURES
* Provides bias for GaAs and HEMT FETs * Drives up to three FETs * Dynamic FET protection * Drain current set by external resistor * Polarisation switch for LNBs -supporting zero volt gate switching topology. * 22kHz tone detection for band switching
APPLICATIONS
*Satellite receiver LNBs * Private mobile radio (PMR) * Cellular telephones
PIN CONFIGURATION
G1 D1 G2 D2 G3 D3 G ND CN B 1 CN B 2 N/ C
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VCC RCA L VP O L FIN N/ C FOUT LOV HB LB CS U B
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PARAMETER
LINEAR INTEGRATED CIRCUIT
SYMBOL
Vcc ICC ID VIN Topr TStg PD
ABSOLUTE MAXIMUM RATINGS
VALUE
-0.6~12 100 0~15 25 continuous -40~70 -50~85 500 Supply Voltage Supply Current Drain Current (per FET) (set by RCAL ) Input Voltage (VPOL) Operating Temperature Storage Temperature Power Disspation(Ta=25C)
UNIT V mA mA V
C C mW
ELECTRICAL CHARACTERISTICS (Ta = 25 C,Vcc=5V,ID=10mA, RCAL =33kUnless otherwise specified)
PARAMETER
Supply Voltage Supply Current
SYMBOL
Vcc ICC
TEST CONDITIONS
ID1 to ID3=0 ID1 =0, ID2 to ID3=10mA,VPOL=14V ID2=0, ID1 to ID3=10mA,VPOL=15.5V ID1 to ID3=0,ILB=10mA ID1 to ID3=0,IHB=10mA (Internally generated) ISUB =0 ISUB = -200A CG=4.7nF,CD=10nF CG=4.7nF,CD=10nF
MIN
5
TYP
6 25 25 16 16 -3
MAX
10 15 35 35 25 25 -2.5 -2.4 0.02 0.005 800
UNIT
V mA mA mA mA mA V V Vpkpk Vpkpk kHz
Substrate Voltage Output Noise Drain Voltage Gate Voltage Oscillator Freq
VSUB
-3.5
END ENG fO
200
350
GATE CHARACTERISTICS
PARAMETER
Output Current Range Output Voltage Gate 1 Off Low High Output Voltage Gate 2 Off Low High Output Voltage Gate 3 Low High
SYMBOL
IGO VG1O VG1L VG1H VG2O VG2L VG2H VG3L VG3H
TEST CONDITIONS
MIN
-30
TYP
MAX
2000
UNIT
A
ID1=0mA, VPOL=14V, IGO1=0A ID1=12mA, VPOL=15.5V, IGO1=-10A ID1=8mA, VPOL=15.5V, IGO1=0A ID2=0mA, VPOL=15.5V, IGO2=0A ID2=12mA, VPOL=14V, IGO2=-10A ID2=8mA, VPOL=14V, IGO2=0A ID3=12mA, IGO3=-10A ID3=8mA, IGO3=0A
-0.05 -2.7 0.4 -0.05 -2.7 0.4 -3.5 0.4
0 -2.4 0.75 0 -2.4 0.75 -2.9 0.75
0.05 -2 1.0 0.05 -2 1.0 -2 1.0
V
V
V
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PARAMETER
Current Current Change With Vcc With Tj Drain 1 Change : High Drain 2 Change : High Drain 3 Change : High Voltage Change With Vcc With Tj Leakage Current Drain 1 Drain 2
LINEAR INTEGRATED CIRCUIT
SYMBOL
ID IDV IDT VD1 VD2 VD3 VDV VDT IL1 IL2 Vcc=5 to12V Tj= -40 to +70C ID1 =10mA VPOL=15.5V ID2 =10mA VPOL=14V ID3 =10mA Vcc=5 to10V Tj= -40 to +70C VD1=0.5V, VPOL=14V VD2=0.5V, VPOL=15.5V
DRAIN CHARACTERISTICS
TEST CONDITIONS MIN
8
TYP
10 0.5 0.05 2.0 2.0 2.0 0.5 50
MAX
12
UNIT
mA %/V %/C V V V %/V ppm
1.8 1.8 1.8
2.2 2.2 2.2
10 10
A
TONE DETECTION CHARACTERISTICS
PARAMETER
Filter Amplifier Input Bias Current Output Voltage 5 Output Current 5 Voltage Gain Rejection Frequency V Threshold 5 Output Stage Lov Volt.Range Lov Bias Current LB Output Low LB Output High HB Output Low HB Output High
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A
IB VOUT IOUT Gv fR FVT VLOV ILOV VLBL VLBH VHBL VHBH
RF1=150k RF1=150k VOUT=1.96V, VFIN=2.1V f=22kHz, VIN=1mV V(AC)IN=1V p/p sq.w6
0.02 1.75 400 1.0 100 -0.5 0.02 -3.5 -0.01 -0.025 2.9 -3.5 -0.01 -0.025 2.9
0.07 1.95 520 46 7.5
0.25 2.05 650
350 Vcc-1.8 1.0 -2.5 0.01 0.025 3.1 -2.5 0.01 0.025 3.1
V A dB kHz mV p/p V A V V V V V V V V
IL=50mA(LB or HB) VLOV=0 VLOV=0, IL= -10A, Enable 6 VLOV=3V, IL=0, Enable 7 VLOV=0, IL=10 mA, Disable 6 VLOV=3V, IL=50mA, Disable 7 VLOV=0, IL= -10A, Disable 6 VLOV=3V, IL=0, Disable 7 VLOV=0, IL=10mA, Enable 6 VLOV=3V, IL=50mA, Enable 7
0.15 -2.75 0 0 3.0 -2.75 0 0 3.0
POLY SWITCH CHARACTERISTICS
PARAMETER
Input Current Threshold Voltage Switching Speed
SYMBOL
IPOL VTPOL TSPOL
TEST CONDITIONS
VPOL=25V (Applied via RPOL=10k) VPOL=25V (Applied via RPOL=10k) VPOL=25V (Applied via RPOL=10k)
MIN
10 14
TYP
20 14.75
MAX
40 15.5 100
UNIT
A V ms
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NOTES: 1. 2. 3. 4. 5. 6. 7.
LINEAR INTEGRATED CIRCUIT
The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CsuB of 47nFare required for this purpose. The characteristics are measured using an external reference resistors RCAL of value 33k wired from pins RCAL to ground. Noise voltage is not measured in production. Noise voltage measurement is made with FETs and gate drain capacitors in place on all outputs. CG,4.7nF,are connected between gate outputs and ground,CD,10nF,are connected between drain outputs and ground. These parameters are linearly related to Vcc These parameters are measured using Test Circuit 1 These parameters are measured using Test Circuit 2
TEST CIRCUIT 1
Vcc + V1 5V DC VPOL FIN Lov GND FOUT CNB1 RCAL CNB2 CSUB CNB 47nF CSUB 47nF RCAL 33K R3 150K R2 CF1 470pF CF2 68pF 10K
V2
+ -
V2 Type Frequency Voltage
Characteristics AC source 22kHz 350mV p/p enabled 100mV p/P disabled
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TEST CIRCUIT 2
LINEAR INTEGRATED CIRCUIT
Vcc + V1 5V DC VPOL FIN Lov GND FOUT CNB1 RCAL CNB2 CSUB CNB 47nF CSUB 47nF RCAL 33K
R5 2.0K CF1 470pF CF2 68pF
R2 10K
R3 150K
V2
+ -
V2 Type Frequency Voltage
Characteristics AC source 22kHz 350mV p/p enabled 100mV p/P disabled
TYPICAL CHARACTERISTICS
Vsub v External Load Vcc =5V -0.0 -0.5 Vsub (V) -1.0 -1.5 -2.0 -2.5 -3.0 20 40 60 Rcal (k) 80 100 0 0.2 Vcc =8V Vcc =10V 1.0 Vcc =5V Vcc =6V Note :Operation with load>200A is not guranteed.
JFET Drain Current v Rcal 16 14 Drain Current (mA) 12 10 8 6 4 2 0 0
0.4 0.6 0.8 External Vsub Load (mA)
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2.2
LINEAR INTEGRATED CIRCUIT
70 60 Open Loop Gain v Frequency Vcc =5V
JFET Drain Voltage v Drain Current
Drain Voltage (V)
2.1
Open Loop Gain (dB) Vcc =10V
50 40 30 20 10 0
2.0
Vcc =5V Vcc =6V Vcc =8V
1.9
1.8 2
4
6
8
10
12
14
16
100
1k
10k 100k Frequency (Hz)
1M
10M
LB/HB Offset Voltage v Load Current Vcc =5V VLOV=0V Open Loop Phase(o) Tamb=70
Open Loop Phase v Frequency Vcc =5V 180 150 120 90 60 30 0 50 100 1k 10k 100k Frequency (Hz) 1M 10M
4 LB/HB Offset Voltage (mV) 2 0 -2 -4 -6 -8 0 10 20 Tamb= -40
Tamb=25
30
40
Load Current (mA) LB/HB Dropout Voltage v Load Current 2.0 1.9 LB/HB Dropout Voltage (V) 1.8 Tamb= -40 1.7 1.6 1.5 1.4 1.3 1.2 0 10 20 30 Load Current (mA) 40 50 Tamb=70 Tamb=25 Vcc =5V Fout Voltage (Vpkpk) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 100 1k
Filter Response
10k 100k Frequency (Hz)
1M
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FUNCTIONAL DIAGRAM
LINEAR INTEGRATED CIRCUIT
+ DN ON GN + 20A CSUB Negative Supply Gen. + I D Set ID Sense VD Set + -
Vcc
RCAL
RCAL SetS ID
GND
CSUB
CNB1
CNB2 CNB
FUNCTIONAL DESCRIPTION
The X3211 provides all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single supply voltage. It contains 3 such stages. The negative rail generator is common to all devices. The drain voltage of the external FET QN is set by the X3211 device to its normal operating voltage. This is determined by the on board VD Set reference, the X3211 provides nominally 2 volts . The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate of the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is usually necessary to drive its gate negative with respect to ground to obtain the required drain current. To provide this capability powered from a single positive supply, the device includes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, CNB and CSUB. The following schematic shows the function of the Vpol input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time, their selection is controlled by the input Vpol. This input is designed to be wired to
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applied to Vpol.
LINEAR INTEGRATED CIRCUIT
the power input of the LNB via a high value (10k) resistor. With th input voltage of the LNB set at or below 14V.FET Q2 will be enabled. With the input voltage at or above 15.5V,FET Q1 will be enabled.The disabled FET has its gate driven to 0V and its drain terminal is switched open circuit.FET number Q3 is always active regardless of the voltage
D1 Q1 G1
Drain voltage& Current Controller
VPOL Input Enable +
20A VSUB D2 Q2 G2 Drain voltage& Current Controller
14.75V Reference
Enable
20A VSUB D3 Q3 G3 Drain voltage& Current Controller
Enable
20A VSUB
Control input switch function INPUT SENSE
<= <= 14 volts 15.5 volts
POLARISATION
Vertical Horizontal
SELECT
FET Q2 FET Q1
For many LNB application tone detection and band switching is required.The X3211 includes the circuitry necessary to detect the presence of a 22kHz tone modulated on the supply input to the LNB.Referrring to the following schematic diagram,the main elements of this detector are an op-amp enabling the construction of a Sallen key filter,a rectifier/smoother and a comparator.Full control is given over the center frequency and bandwidth of the filter
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protection of pin Vpol ).
LINEAR INTEGRATED CIRCUIT
LOV
by the selection of two external resistors and capacitors (one of these resistors,R2, shares the functionof overvoltge
Input + Enable
LB
Output
VSUB CF2 68pF LNB input R2 10k CF1 470pF FILTER FOUT R3 150k FIN + REF1
DETECTOR COMPARATOR
+ Enable D1 + C1 REF2 OUTPUT DRIVERS VSUB
HB Output
APPLICATION CIRCUIT
*L1 C2 Q1 *C2 10nF *L2 *C3 CG 4.7nF DN *Stripline Elements GN Vcc HB VPOL FIN LB LOV FOUT
GND CNB1 RCAL CNB 47nF
CNB2 CSUB CSUB 47nF
RCAL 33K
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gate drain capacitors in circuit.
LINEAR INTEGRATED CIRCUIT
FETs and
APPLICATIONS INFORMATION
The device is a partial application circuit for the X3211 showing all external components required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with the associated
Capacitors CD and CG ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF feedthrough between stages via the X3211. These capacitor are required for all stages used Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nFand 100nF could be used. The capacitors CNB and CSUB are an integral part of the X3211 negative supply generator. The negative bias voltage is generated on-chip using an internal oscillator. The required value of capacitors CNB and CsuB is 47nF. This generator produces a low current supply of approximately -3 volts. Although this generator is intended purely to bias the external FETs, it can be used to power other external circuits via the CsUB pin. Resistors RcAL sets the drain current at which all external FETs are operated. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without affecting the operation of the remaining bias circuits. The X3211 has been designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3.5V to 1V,under any conditions including power up and powerdown transients. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current. Tone detection and band switching is provided on the X3211. The following diagrams describes how this feature operates in an LNB and the external components required. The presence or absence of a 22kHz tone applied to pin FIN enables one of two outputs, LB and HB.A tone present enables HB and tone absent enables LB. The LB and HB outputs are designed to be compatible with both MMIC and discrete local oscillator applications, selected by pin LOV. Referring to Figure 1 wiring pin LOV to ground will force LB and HB to switch between -2.6V (disabled) and 0V (enabled).Referring to Figure 2 wiring pin LOV to a positive voltage source (e.g. a potential divider across Vcc and ground set to the required oscillator supply,Vosc when enabled. Tone Detection Function LOV
FIN
22kHz 22kHz -
LB
Disabled Enabled Disabled Enabled
HB
Enabled Disabled Enabled Disabled
LB
-2.6 volts GND Note 1 Vosc
HB
GND -2.6 volts Vosc Note 1
GND GND
Note 1: 0 volts in typical LNB applications but dependent on external circuits.
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LINEAR INTEGRATED CIRCUIT
Vcc CF1 R2 LNB Downfeed 10k
APPLICATIONS INFORMATION (cont)
X3211 1 G1 D1 G2 D2 G3 D3 GND CNB1 CNB2 N/C Vcc RCAL VPOL FIN N/C FOUT LOV HB LB CSUB CUB 47nF R1 33k R3 150k
470pF CF2 68pF Vcc
R4 10 R5 10
CNB 47nF
Local CHB Osc. 100nF G1 MMIC CLB 100nF
G2
Figure 1 Lov grounded Vcc CF1 1 X3211 G1 D1 G2 D2 G3 D3 GND CNB1 CNB2 N/C Vcc RCAL VPOL FIN N/C FOUT LOV HB LB CSUB CUB 47nF R1 33k R3 150k 470pF CF2 68pF R4 10 R5 9.75GHz Local Osc R7 3k 10 CLB 100nF R9 CHB 100nF 10.6GHz Local Osc LNB Downfeed
R2 10k
CNB 47nF
R8
Figure 2 Lov connected to Vosc
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LINEAR INTEGRATED CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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